The present invention generally relates to routing in computer networks and, more specifically, to a method and system for optimizing routing functions in routers with a split plane architecture.
A router typically has three basic components, namely, a routing table, a forwarding information base (FIB) and an address resolution protocol (ARP) cache. The routing table contains information relating to routers that are present on a computer network. The FIB contains information that is necessary to forward an Internet Protocol (IP) datagram to its intended destination, i.e., the FIB contains information on paths or routes that can be used to forward the IP datagram. The ARP cache includes information relating to mappings from IP addresses to corresponding hardware addresses. ARP provides a dynamic mapping between two different forms of addresses: an IP address and whatever type of address a data link uses. ARP is used to resolve a layer-3 IP address to a layer-2 MAC address.
In a software based router, when a datagram or packet needs to be forwarded, the router consults the FIB. Once a route for the packet is identified, the router then consults the ARP cache to retrieve the MAC address of the next hop gateway or host. If a corresponding MAC address is located in the ARP cache, the packet is forwarded to the next hop gateway using the corresponding MAC address. Otherwise, an ARP request is initiated to resolve the needed corresponding MAC address. A reply to the ARP request from the next hop gateway provides the needed corresponding MAC address that can then be used to forward the packet. An appropriate entry linking the IP address and the corresponding MAC address is then stored in the ARP cache. Subsequent packets that need to pass through the same gateway can be quickly forwarded using the recently added entry in the ARP cache. To account for gateways or hosts that become unavailable, the ARP cache entries are invalidated after a predetermined period of time. This prevents the router from forwarding packets to a gateway or host that is not operational, thereby minimizing waste of network resources. At the same time, periodic invalidation of the ARP cache entries also saves precious memory resources of the router as the router no longer has to maintain any information relating to the next hop.
In traditional software based routers, the functions of the three basic components of the router are performed by software. Recently, due to advances in hardware technologies, many router vendors have utilized a split plane architecture which segregates or splits the forwarding functions from the routing functions. In other words, the split plane architecture includes a control plane and a data plane. The control plane determines and controls how a packet is to be routed or forwarded; and the data plane performs the actual forwarding of the packet. With the split plane architecture, the forwarding functions are implemented in hardware, for example, network processors, in order to achieve line rate forwarding as high as, for example, OC-48 or even OC-192. However, the split plane architecture has its own set of issues that are not present in the traditional software based routers.
One of the common problems encountered in the split plane architecture is, for example, delay in determination of routes. In the split plane architecture, the hardware (for example, the network processor) requires that all information that is necessary for forwarding a packet be programmed in advance before the packet arrives for delivery to its intended destination. As a result, routes traversing a gateway, whose ARP cache entries are not resolved, are not programmed. When a packet is received for delivery to an intended destination for which the ARP is not resolved, the network processor forwards the packet to the control plane which, in turn, generates an ARP request. As a result, upon the arrival of a packet intended for a particular destination whose ARP is not resolved, ARP needs to be engaged and the proper route entries need to be programmed, thereby incurring delay in the delivery of the packet. Once the ARP is resolved, the route entries are programmed with the complete information. Subsequent packets can then be forwarded by the network processor without any assistance from the control plane. One drawback of performing address resolution only upon arrival of a packet is that the packet cannot be delivered while address resolution is being performed. That increases the likelihood of losing that packet. For example, on a 10 Mbps pipe, a network processor can forward about 20,000 packets/sec (each packet being 64 bytes long). It takes about 1-2 seconds to resolve an ARP entry. During this 1-2 second period, the number of packets lost can reach about 20,000 to 40,000 packets for each route that does not have an ARP entry resolved.
Another common problem encountered in the split plane architecture is ARP cache invalidation. As previously mentioned, ARP cache entries are periodically invalidated. Hence, when an ARP cache entry times out or becomes invalidated, all the route entries in the network processor that relate to that particular ARP cache entry have to be flushed or deleted. Consequently, the ARP cache entry has to be re-learned again and the corresponding routes reprogrammed again in the network processor. The re-learning and reprogramming operations consume significant CPU resources and time. Empirically, it has been shown that it takes about 2-3 minutes to program 5000 routes. During this time, packets received for routes that have not been programmed are either dropped or sent to the CPU, thereby negatively affecting forwarding performance.
Hence, it would be desirable to provide a method and system that is capable of optimizing route determination and routing table changes due to ARP cache invalidation in routers with a split plane architecture.